Well the meme says to add some new layer over syscalls so the plan is already to break userspace entirely to force you to make a new one. But yeah if you wanted to make it irl bundling another kernel would likely be easier then Linux unless you wanted the hw support.
Look, honestly this has merit. Not for Claude Code, that’s insane. But there are a lot of Risc V capable NPUs that could use a smaller model for internal locally sourced workflows. I’m thinking like a read only RAG paired with a tiny GLM 4.7 trimmed down to fit on a SpacemiT Key Stone K3.
Also RUST is a lot easier to implement on RISC-V hardware, and I would suggest it as it’s more memory safe on most hardware, especially since often a user can get to Ring 0 with little trouble
Well the meme says to add some new layer over syscalls so the plan is already to break userspace entirely to force you to make a new one. But yeah if you wanted to make it irl bundling another kernel would likely be easier then Linux unless you wanted the hw support.
Look, honestly this has merit. Not for Claude Code, that’s insane. But there are a lot of Risc V capable NPUs that could use a smaller model for internal locally sourced workflows. I’m thinking like a read only RAG paired with a tiny GLM 4.7 trimmed down to fit on a SpacemiT Key Stone K3.
I’ll reference you on Codeberg.
https://www.cnx-software.com/2026/01/23/spacemit-k3-16-core-risc-v-soc-system-information-and-early-benchmarks/ woah these do seem cool
Yup, here’s a good read if you get the chance. https://riscv.org/blog/risc-v-upstreaming/
Also if you’d like to start in the middle this is interesting as well https://www.sifive.com/blog/all-aboard-part-7-entering-and-exiting-the-linux-kernel-on-risc-v
Also RUST is a lot easier to implement on RISC-V hardware, and I would suggest it as it’s more memory safe on most hardware, especially since often a user can get to Ring 0 with little trouble
https://github.com/xiaoyang-sde/rust-kernel-riscv