The RISC-V vector C intrinsics provide users interfaces in the C language level to directly leverage the RISC-V “V” extension (RISC-V “V” Vector Extension, n.d.) (also abbreviated as “RVV”), with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also aim to free users from responsibility of maintaining the correct configuration settings for the vector instruction executions. This document uses the term “RVV” as an abbreviation for the RISC-V “V” extension. This document uses the term “the RVV specification” to indicate the RISC-V “V” extension specification.